1. Technical Field
The present invention relates to a primary serial bus coupled to multiple secondary serial buses in general, and in particular to an I2C primary bus coupled to multiple secondary I2C buses. Still more particularly, the present invention relates to an apparatus for supporting I2C bus masters on a secondary side of an I2C mulitplexor.
2. Description of the Related Art
An inter-integrated circuit (I2C) bus is a well-known industry standard serial bus for interconnecting various integrated circuit devices within a data processing system. A standard I2C bus includes two lines, namely, an SDA line and an SCL line. The SDA is for transmitting start, address, data, control, acknowledge and stop information, and the SCL line is for carrying a clock signal.
Generally speaking, a bus master transmits a start bit followed by 8 bitsxe2x80x947 address bits and 1 read/write bit. Of the 7 address bits, 4 bits are preprogrammed by a chip manufacturer, and the remaining 3 bits are typically programmed by a system manufacturer. Because the chip manufacturer pre-programs the most significant 4 bits of a 7-bit address, leaving only 3 programmable address bits for the system manufacturer, an electronic system is usually limited to having a maximum of 23 (i.e., 8) of the same type of chip connected to any one I2C bus.
Following the transmission of the address and read/write bits, the addressed bus slave responds with an acknowledge (ACK) bit. Next, the bus master transmits 8 bits of data, which is again followed by the transmission of an ACK from the bus slave. The pattern of 8 data bits followed by an ACK bit can be repeated until all data has been transmitted. The transmission can be terminated at any time via a transmission of a stop bit.
Bus loading is a limitation as to the total number of devices that can be coupled to any one bus. Because of bus loading and the intrinsic inability to address more than 8 of the same type of chip on any one I2C bus, system manufacturers have previously incorporated more than one I2C bus, and there are two general approaches to interconnect multiple I2C buses within an electronic system.
The first approach is to use multiple primary I2C buses, each with its own controller. Although the first approach solves the problems of bus loading and address availability, it requires additional I2C controllers that are usually the most expensive device in an electronic system having an I2C bus. In addition, the requirement of running multiple primary I2C buses through many connectors and interfaces adds cost and, in some cases, is not possible because of the limited pin count of the connectors and interfaces.
The second approach is to use one primary I2C bus multiplexed with two or more secondary I2C buses, but controlled separately from any of the secondary I2C buses. The second approach is an improvement over the first approach because it does not require additional controllers and it is not constrained to run through multiple connectors and interfaces. However, a separate mechanism must be set up to control the multiplexing. In addition, since the primary I2C bus is switched under the second approach, it must be controlled from a different primary I2C bus; otherwise, data loss and signal quality degradation will occur. The need for more than one primary I2C bus limits the total benefits of the second approach.
Furthermore, the original I2C mulitplexor was generally lacking support for multiple bus masters on the secondary side of the I2C mulitplexor. If an I2C bus master was placed on the secondary side of the I2C mulitplexor, a bus collision might occur if there was master activity on the secondary side and the I2C mulitplexor were switched to that particular secondary I2C bus. A straight-forward solution to the above-mentioned problem is to remove the offending secondary I2C bus master, but a better solution is preferred.
The present disclosure provides an improved method and apparatus to support I2C bus masters on a secondary side of an I2C mulitplexor.
In accordance with a preferred embodiment of the present invention, an electronic system includes a primary serial bus, multiple secondary serial buses, an expander, multiple direction latches, a multiplexor, multiple busy detect circuits, and a to-from multiplexor circuit. The expander, which is coupled to the primary serial bus, includes multiple outputs that can be selectively activated. Each of the direction latches is coupled to a respective one of the outputs of the expander. The multiplexor, which is coupled to the direction latches, includes several outputs connected to the secondary serial buses such that the secondary serial buses can be selectively connected to the primary serial bus. Each of the busy detect circuits is coupled to a respective one of the outputs of the multiplexor. The busy detect circuits detects if there is a transaction occurring on one of the outputs of the multiplexor. In response to a transaction occurring on one of the outputs of the multiplexor, the to-from multiplexor circuit selects one of the busy detect circuits that is involved in the transaction in order to allow one of the direction latches to latch at a correct time such that any bus corruption on the secondary serial buses can be avoided.
All objects, features, and advantages of the present invention will become apparent in the following detailed written description.